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The possibility for distribution of FPGA resources in the temporal domain for multi-modal & multi-task workloads conceptually allows virtualization of logic, communication and input/output resources similar to memory virtualization in advanced conventional computers (e.g. superscalar). This, in turn, can dramatically increase the cost-effectiveness of FPGA based reconfigurable computing systems...
The conception of Network-on-Chip (NoC) presents system designers with a new approach to the design of on-chip interconnection structures. However, such networks present designers with a large array of design parameters and decisions, many of which are critical to the efficient operation of NoC systems. To aid the design process of complex systems-on-chip, this paper presents a NoC simulation environment...
The concept of hardware resource virtualization which was initiated in virtual memory organization has recently expanded towards virtualization of computing resources in partially reconfigurable FPGAs. However, this kind of resource virtualization requires mechanisms for flexible allocation/relocation of components associated with data execution processes. The ability for on-chip component relocation...
This paper presents a new approach to meeting communication requirements of on-chip network systems. The method is based on the transaction-oriented protocol employed by on-chip components, and the fact that latency becomes the performance-impacting factor instead of bandwidth. A network-on-chip topology generation and analysis tool is presented which has the primary aim of generating on-chip topologies...
This paper presents a new approach to the design and analysis of NoC topologies which is based on the transaction-oriented communication methods of on-chip components. We propose two algorithms that attempt to meet the communication requirement of an on-chip application using a minimum number of network resources for the task, by generating application-specific topologies. In addition, to aid the...
This paper presents a network-on-chip transaction simulator with the aim of providing early performance estimation for a given application. The simulator is an example of communication centric simulation and requires reduced characterization of a given system to provide performance results. It incorporates spatial access patterns and device response speeds to accommodate a wide range of embedded system...
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