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This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected...
In this paper, an SET and SEU tolerant latch suitable for use in embedded systems called SETUR (single event transient and upset robust latch) is presented and evaluated. The SETUR is based on the use of a redundant feedback line and a CMOS delay element to tolerate the effect of the SETs occurring in the input line of the latch as well as SEUs occurring inside the latch. The experimental results...
High reliability, low power consumption and high performance are key objectives in the design of NoCs. These three design objectives should be considered simultaneously in order to have an optimal design. This paper proposes a method to reduce power consumption of an application specific NoC. This is done in two steps: 1) Extra virtual channels are used in the router architecture to increase the performance...
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