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In this paper, based on the temperature calculation in block-level thermal model, a two-phase approach is proposed to reduce the final floorplan temperature by redistributing the white space in all the device layers and inserting the thermal vias onto the available white space. The experimental results show that our proposed approach reduces 5.5%, 11.3% and 20.5% of temperature on 100%, 110% and 120%...
Designs with non-tree consideration have been proven to improve the yield and reliability in modern chips. In this paper, an efficient three-phase approach for transformation-based timing analysis is proposed to transform a cyclic graph into an acyclic graph by using the node-splitting operation and compute the delay of the transformed tree-based circuit in an Elmore delay model. Compared with the...
Thermal issues have become a determinant factor to result in very large scale integrated (VLSI) circuits work or malfunction. For this reason, the paper proposed an efficient block-level thermal model for temperature calculation in the floorplan stage among the integrated circuit (IC) design flow. Furthermore, the model accurately profiles the temperature difference between all thermal blocks and...
Given an LB-compact floorplan, a 3D block-level thermal model is firstly proposed to calculate the temperature of each circuit block in reasonable time. Furthermore, based on the temperature calculation in the proposed 3D block-level thermal model and the final floorplan region, an iterative approach is proposed to reduce the final floorplan temperature by inserting or redistribution the feasible...
In this paper, given a set of connecting nodes in a signal net, based on the result of optimal wire width and buffer insertion in a wire segment (Yan, 2006) and the concept of sharing-buffer insertion and hidden Steiner-point assignment, an effective tree construction approach is proposed to construct a timing-driven rectilinear Steiner tree with wire sizing, buffer insertion and obstacle avoidance...
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