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A power-efficient low-voltage buffer is presented. The proposed buffer contains a low-frequency zero generation circuit to perform frequency compensation and a slew-rate enhancement (SRE) circuit to provide large dynamic current for driving the pass device of the low-dropout (LDO) voltage regulator. Whatpsilas more, the proposed buffer, consuming small quiescent current over full load range, can work...
1.0-V, 50-mA capacitor-less low-dropout (LDO) voltage regulator with 100pF internal output capacitor for SoC applications is presented. The proposed LDO makes use of a bi-directional asymmetric buffer (BDAB), which provides a signal inversion feedback path and a signal non-inversion feedforward path with different magnitudes at the same time. The feedback path can perform frequency compensation and...
High-stability, high-accuracy low-dropout (LDO) voltage regulators are presented. The proposed LDOs make use of the slow-rolloff frequency compensation scheme which can enhance the stability, increase the loop gain and unit-gain frequency (UGF). This scheme is realized by introducing a dominant half-pole by virtue of three zero-pole pairs and a low-frequency pole. Post-layout simulation results show...
Utilizing a novel unit-gain compensation cell (UGCC) to perform frequency compensation and power supply rejection (PSR) enhancement, a low-voltage high-PSR low-dropout regulator (LDO) is presented in this paper. The proposed UGCC, consisting of a 1 pF on-chip capacitor and six transistors, effectively overcomes the drawbacks that exist in the conventional compensation schemes by generating an internal...
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