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The design and characterization of CMOS compatible medium voltage LDMOS transistors are presented. Devices of different sizes were fabricated in a 0.25 μm BiCMOS technology and were characterized in the most important wireless telecommunication bands up to 5.8 GHz using a load/source pull measurement setup. Alternative layouts with regards to device geometry and stabilizing networks were investigated...
In this contribution, design of a 4W GaN HEMT power amplifier (PA) for C-band application for instance of Car to Car communications will be reported. The PA design procedure considers the characteristics of digital modulated signals planned to be used in C-Band. Such signals have a high peak to average ratio (PAR), which requires highly efficient and linear PA. A 4W low cost and small size class-AB...
In this paper the design of a 2 W uneven C-band Doherty power amplifier is presented. The Doherty PA is designed to achieve high efficiency for digitally modulated signals with high peak to average power ratio (PAR) used in wireless local area network (WLAN) systems around 5.6 GHz. The Doherty amplifier has been designed using two equal sized GaAs devices for the main Class- AB and peaking Class-C...
In this paper, the skin effect of on-chip transmission lines and inductors at K-Band operating frequencies are investigated. Two microstrip lines with different lengths are simulated and compared with each other. A patterned ground shielded inductor is simulated using various meshing strategies and the results are compared. A 24 GHz common source CMOS low noise amplifier is designed, simulated and...
A fully integrated 2 stage K-band power amplifier is designed, fabricated and measured. The amplifier is realized utilizing standard 0.18 μm CMOS process. A novel simplified matching and bias network is used in order to reduce the input and output losses and to achieve a high output power and PAE. At 24 GHz, the measured results of the amplifier are, a small-signal power gain of 16.2 dB, a maximum...
This paper presents a fully integrated V-band two stage power amplifier with cascode topology. The PA is designed on 0.25 ??m SiGe:C BiCMOS technology. The technology provides ft and fmax ?? 200 GHz. The two stage PA provides a gain of 17 dB at 64 GHz. The PA has been optimized for biasing circuit, PA Core and the matching networks. This has resulted in high power and high linearity from 58 GHz to...
This paper presents a high efficiency uneven UMTS Doherty power amplifier (DPA) based on Si LDMOS technology. An optimum output combining network was designed to enhance the efficiency at backoff power. High efficiency Si LDMOS transistors were used for the DPA design. The designed DPA has a maximum output power of Psat=39.7 dBm (9.4 W). A maximum drain efficiency of ??max=54% (PAEmax=40%) was measured...
This paper, presents the design and evaluation of a high efficiency, 30 W, two-stage, power amplifier for the 2.45 GHz ISM band. The designed amplifier targets an industrial application where precise control over the output power with good efficiency is necessary. A saturated output power of 44.7 dBm (30 Watts) was reached at a maximum drain efficiency of 67.8%. A full 5 dB control of the output power...
This paper presents a fully integrated 60 GHz single stage power amplifier with cascode topology. The PA is designed on 0.25 mum SiGe:C BiCMOS technology. The technology provides ft and fmax ap 200 GHz. The PA has achieved the 1 dB gain bandwidth of more than 9 GHz from 57 GHz to 66 GHz and 3 dB gain bandwidth of more than 18 GHz (30 %) from 51 GHz to 69 GHz. The PA has been designed to have the wideband...
A fully integrated 5.6-6.4 GHz power amplifier is implemented in a 0.25 mum SiGe-HBT technology using an on-chip transformer combining structure. The novel combiner topology combines the output power of two push pull pairs and leads to a reduced transistor size compared to a conventional combiner while enhancing the efficiency and maintaining the maximum output power. Electromagnetic modeling of the...
In this work a broad-band class E power amplifier (PA) is designed, manufactured and measured. 400 MHz bandwidth with a center frequency of 800 MHz was realized using a GaN HEMT device. A novel and easy circuit topology is proposed for broad-band bandpass filter with integrated output matching network. Different filter types are discussed, suitable topology is chosen and design equations are shown...
A fully integrated CMOS receiver consisting of an LNA and a mixer has been designed and fabricated in IBM BiCMOS 7WL 180 nm technology. An on-chip balun loading the second stage of the LNA was implemented as well for single-to-differential conversion. The receiver was developed for high performance wireless local positioning systems and excellent experimental results were demonstrated: a conversion...
In this paper, a 6W uneven LDMOS Doherty power amplifier (DPA), designed for GSM900 base stations, which implement phased antenna array transmission, is presented. The designed Doherty PA can deliver a maximum power of 6.5W. A high drain efficiency of eta=64% (PAE=58%) is measured. The efficiency is maintained above eta=43% (PAE=37%), over 6-dB output backoff, and above eta=31% (PAE=29%), over 9-dB...
A digitally controlled variable gain amplifier (VGA) for low power, low-IF receivers is presented. The amplifier was designed and fabricated in IBM 7WL BiCMOS 180 nm technology. It shows a dynamic range of 45 dB with a maximum gain of 52 dB and a minimum gain of 7 dB. The gain variation is achieved by means of switched feedback resistors. These are controlled by a demultiplexer and 4 control bits...
This work presents a Class F-1 power amplifier (PA) operating at 2.35 GHz. An output power of 40 W (46 dBm) was achieved with 10 dB gain. The maximum drain efficiency was measured to be 60.8% (PAE = 55.7 %). The power amplifier was implemented using GaN pHEMT. The realization of the optimum load resonator was designed by a microstrip resonator, for the first four harmonics. The resonator achieves...
This paper exhibits a 10 W class AB highly linear power amplifier (PA) for a frequency of 2.14 GHz using GaN HEMT. Power and linearity measurements and simulations illustrate stupendous correspondence. An output power of 11 W (41 dBm) with maximum drain efficiency (eta) of 72 % (PAE 56 %) is achieved. Linearity measurements were made with a frequency spacing of 100 KHz and output third-order and second-order...
Modern wireless communication standards, e.g. UMTS, are making use of modulation schemes, resulting in signals with high levels of peak-to-average power ratio (PAR). For example, the W-CDMA signal used in UMTS-standard has typical PAR levels above 6 dB. Conventional single-ended power amplifiers will result in low levels of average efficiency, if they were implemented in the transmitters of such communication...
In this work we present a fully integrated BiCMOS RF-receiver. The receiver comprises an LNA and a mixer. The most challenging aspects of the design were the high gain and an extremely low noise figure specified by RESOLUTION. The target was to achieve an integrated LNA and mixer showing at least 25 dB voltage conversion gain and overall noise figure less than 4 dB under minimum power consumption...
Through this work we highlighted and demonstrated the significance of an algorithmic way of design and development of CMOS LNAs at 5 GHz. The systematic design led to very good measured performances of 14 dB gain, 1.78 dB noise figure, 10 dB return loss both at the input and output and a high linearity of-3 dBm of IP3 under 5.4 mW power consumption. These results compare the best performances reported...
A fully integrated broadband push-pull power amplifier (PA) has been developed and fabricated in a 0.25 mum SiGe-HBT technology. Monolithic transformers are used to transform the 50 iquest input/output of the amplifier to the optimum load and source impedances of an efficient push-pull pair. Electromagnetic modeling of the whole chip structure has been carried out in order to optimize the performance...
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