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This paper evaluates the transformer and capacitor coupling used in W-band broadband CMOS power amplifiers. Therefore two four-stage differential power amplifiers were implemented in 40 nm CMOS technology one with transformer coupling and one with capcitor coupling. In order to achieve broadband performance a complex output matching network consisting either of transmission lines and transformer or...
In this paper the design and measurement of a four stage broadband differential power amplifier intended for W-band using 40 nm bulk CMOS is presented. In order to achieve broadband performance a complex output matching network consisting of transmission line elements and transformers is employed. Furthermore capacitive cross-coupling neutralization is introduced to enhance the stability and the small-signal...
In this paper a GaN-HEMT Doherty amplifier targeted for vehicular applications at 6 GHz is presented. The harmonic tuning of the selected bare-die transistors was investigated and implemented in order to improve the overall large-signal performance. The Doherty amplifier was studied and optimized on device reference plane level using two equally sized 8-Watt GaN devices for the main class-AB and the...
The design and characterization of CMOS compatible medium voltage LDMOS transistors are presented. Devices of different sizes were fabricated in a 0.25 μm BiCMOS technology and were characterized in the most important wireless telecommunication bands up to 5.8 GHz using a load/source pull measurement setup. Alternative layouts with regards to device geometry and stabilizing networks were investigated...
A fully integrated 2 stage K-band power amplifier is designed, fabricated and measured. The amplifier is realized utilizing standard 0.18 μm CMOS process. A novel simplified matching and bias network is used in order to reduce the input and output losses and to achieve a high output power and PAE. At 24 GHz, the measured results of the amplifier are, a small-signal power gain of 16.2 dB, a maximum...
This paper presents a fully integrated V-band two stage power amplifier with cascode topology. The PA is designed on 0.25 ??m SiGe:C BiCMOS technology. The technology provides ft and fmax ?? 200 GHz. The two stage PA provides a gain of 17 dB at 64 GHz. The PA has been optimized for biasing circuit, PA Core and the matching networks. This has resulted in high power and high linearity from 58 GHz to...
This paper presents a fully integrated 60 GHz single stage power amplifier with cascode topology. The PA is designed on 0.25 mum SiGe:C BiCMOS technology. The technology provides ft and fmax ap 200 GHz. The PA has achieved the 1 dB gain bandwidth of more than 9 GHz from 57 GHz to 66 GHz and 3 dB gain bandwidth of more than 18 GHz (30 %) from 51 GHz to 69 GHz. The PA has been designed to have the wideband...
A fully integrated 5.6-6.4 GHz power amplifier is implemented in a 0.25 mum SiGe-HBT technology using an on-chip transformer combining structure. The novel combiner topology combines the output power of two push pull pairs and leads to a reduced transistor size compared to a conventional combiner while enhancing the efficiency and maintaining the maximum output power. Electromagnetic modeling of the...
A digitally controlled variable gain amplifier (VGA) for low power, low-IF receivers is presented. The amplifier was designed and fabricated in IBM 7WL BiCMOS 180 nm technology. It shows a dynamic range of 45 dB with a maximum gain of 52 dB and a minimum gain of 7 dB. The gain variation is achieved by means of switched feedback resistors. These are controlled by a demultiplexer and 4 control bits...
This work presents a Class F-1 power amplifier (PA) operating at 2.35 GHz. An output power of 40 W (46 dBm) was achieved with 10 dB gain. The maximum drain efficiency was measured to be 60.8% (PAE = 55.7 %). The power amplifier was implemented using GaN pHEMT. The realization of the optimum load resonator was designed by a microstrip resonator, for the first four harmonics. The resonator achieves...
A 60 GHz SiGe HBT chipset for high speed wireless communication systems has been developed. The functionalities of LNA, up-converter, down-converter and PA have been realized with good performance. Design strategy, achieved results and comparison with state-of-the-art work will be presented. The work proves that single chip integration of the whole 60 GHz RF-frond-end will be possible using silicon...
A folded double-balanced mixer has been implemented in a 0.18 mum BiCMOS technology for wireless local positioning applications. Operating in the unlicensed ISM band centred at 5.8 GHz with a 150 MHz bandwidth and with a very low IF frequency band from 500 kHz up to 5 MHz, the mixer achieves 17 dB voltage conversion gain, 8.5 dB noise figure and input IP3 of - 6 dBm. The mixer power consumption is...
A two stage bipolar low noise amplifier based on common-emitter configuration is presented in this work. From transistor size scaling to complete two stage integration, various design aspects and issues will be investigated. It will be shown that by following the proposed design methodology, the input as well as the interstage matching of the low noise amplifier (LNA) can be highly simplified without...
In this work we report on the importance of electromagnetic analysis for the layout design of monolithic 60 GHz power amplifiers (PA) in SiGe HBT technology. To facilitate this, two different layouts of the same circuit architecture were investigated. The circuits were originally designed using the circuit simulator of Agilentpsilas ADStrade and realized in a high performance 0.25 mum SiGe BiCMOS...
A folded Gilbert cell mixer has been implemented in a 0.13 mum CMOS technology. RF- and IF- frequencies of the down conversion mixer were 5.5 GHz and 500 MHz, respectively. A power conversion gain of 4.6 dB and a noise figure of 14.2 dB have been demonstrated experimentally under very low power consumption, only 4.2 mW for the mixer core. Considering the overall performances of the circuit, this paper...
A monolithic low-noise-amplifier operating in the 60 GHz band is presented. The circuit has been designed utilizing an advanced 0.25 mum SiGe BiCMOS technology, featuring npn transistors with fT and fmax ap 200 GHz. A two stage cascode architecture has been chosen for the implementation. Design techniques and optimization procedure are explained in detail. Measurements show a gain of 18 dB at 61 GHz,...
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