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High-speed differential interfaces implementing specific solutions for low-power consumption and low-EMI disturbances are vastly used in mobile platforms. In these devices, the slew rate is suitably controlled, the communication scheme alternatas data-bursts followed by power-saving states, the voltage swing and the common-mode level are reduced. To achieve these targets, a key role in voltage-mode...
For over a decade, buffer macromodeling has been a topic of great interest for the integrated circuit industry. The performance assessment of high-speed datalinks requires efficient means of simulating IC ports making compact and accurate behavioral models valuable instruments. In the present communication a new modeling technique, with several important advantages is described. The approach is purely...
High-speed differential interfaces implementing specific solutions for low-power consumption and low-EMI disturbances are vastly used in mobile platforms. In these devices, the slew rate is suitably controlled, the communication scheme alternates data-bursts followed by power-saving states, the voltage swing and the common-mode level are reduced. To achieve these targets, a key role in voltage-mode...
This paper addresses the behavioral modeling of digital drivers for Signal and Power Integrity co-simulations. State-of-the-art two-piece model representations are combined with a compact description of the device static characteristics. The latter are considered as multivariate mappings that are functions of the device electrical variables, and of additional parameters defining process corners and...
This paper presents innovative compressed macro-models of high-speed digital transceivers for system-level Signal and Power Integrity co-simulations. These simulations assume a paramount importance for the design of modern, low-cost and highly integrated systems. An excellent accuracy and an outstanding run-time speed-up are demonstrated by applying the macromodeling methodology to a state-of-the-art...
This paper addresses the prediction of eye diagrams in high-speed data links with the inclusion of manufacturing tolerances. The statistical assessment of the system performance is done via the combined application of accurate and efficient IC models and of the stochastic collocation method with Lagrange interpolating polynomials. Numerical results on the computation of the eye opening profile for...
In previous papers [1,2] the authors have investigated the use of Volterra series in the identification of IC buffer macro-models. While the approach benefited from some of the inherent qualities of Volterra series it preserved the two-state paradigm of earlier methods (see [3] and its references) and was thus limited in its versatility. In the current paper the authors tackle the challenge of going...
This paper addresses the simulation of carbon nanotube interconnects with the inclusion of the effects of parameter uncertainties due to the fabrication process. The proposed approach is based on the available state-of-the-art models of nanointerconnects and on the expansion of the voltage and current variables in terms of orthogonal components, leading to an enhanced stochastic model. The method...
The modeling of the core power-delivery network of digital integrated circuits (ICs) is addressed by a black-box approach, leading to an n-port equivalent of the IC. The model parameters are estimated from external measurements carried out at the IC ports. The modeling procedure is demonstrated for a commercial NOR Flash Memory in 90 nm technology housed by a specifically-designed test fixture.
This paper presents a Volterra-based method of behavioral modeling for the I/O buffers of digital ICs. While this technique brings a slight improvement in accuracy over previous ones, its main strength is a greater degree of generality. With a modeling approach less dependent on the nature of the devices and more easily extendable to include the effects of multiple inputs one may hope better meet...
This paper addresses the generation of enhanced behavioral models for digital IC buffers. The proposed models can reproduce the behavior of real devices also for large fluctuations of the power supply voltage. The models can be easily estimated from port transient responses and can be effectively implemented in any commercial tool as SPICE subcircuits or VHDL-AMS descriptions.
This paper addresses the generation of accurate macromodels of digital ICs accounting for both the functional and the out-of-band behaviour of devices. The proposed models that can be effectively used for immunity predictions are obtained from port transient responses only and can be implemented in any commercial tool based on SPICE or mixedsignal hardware description languages. The approach is demonstrated...
In this paper enhancements of parametric behavioral models for the output buffers of digital ICs are explored. A model based on a single-piece structure, which offers improved accuracy in describing state transition events for arbitrary load conditions, is proposed. This model exploits the potentiality of local-linear state-space parametric relations. These relations can be effectively estimated from...
This paper addresses the development of accurate and efficient macromodels of the output ports of digital integrated circuits. The proposed approach is based on the estimation of mathematical parametric relations reproducing the external behavior of devices from transient port voltage and current responses recorded during the normal activity of the IC. The efficiency of the approach is demonstrated...
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