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A double-heterojunction bipolar transistor having a degenerately doped emitter layer is investigated. The base-emitter Esaki diode introduces very low input impedance in the off- state but does not degrade the current gain at high forward bias. The heavily doped emitter layer makes it possible to scale the emitter-layer thickness considerably. The heavily doped emitter layer also allows contacting...
We present a high linearity 2-bit digital-to-analog converter (DAC) implemented in an InP/GaInAs DHBT technology. The DAC is based upon the current steering architecture. Cascode structure and layout techniques, i.e. static shuffling and dummy devices, have been used to enhance the linearity. The DAC exhibits static integral/differential nonlinearities of 5.5 × 10-3 LSB, equivalent to a resolution...
We present simulations and measurements of the sensitivity of a master-slave emitter-coupled logic (ECL) latched comparator implemented in an InP/GaInAs DHBT technology. The circuit exhibited simulated and experimental sensitivities of 11.5 mV and 17 mV, respectively, at a clock rate of 20 GHz, with no preamplifier.
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