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This article describes test development for embedded mixed-signal and RF modules in core-based design. The test development approach is fully automated and encompasses a DFT architecture that supports an arbitrary test method. Fully compliant with existing IEEE test standards, the proposed approach has been used for test development and characterization of mixed-signal cores in several industrial...
The single stuck-at fault coverage is often seen as a figure-of-merit also for scan testing according to other fault models like transition faults, bridging faults, crosstalk faults, etc. This paper analyzes how far this assumption is justified. Since the scan test infrastructure allows reaching states not reachable in the application mode, and since faults only detectable in such unreachable states...
Chip structures shrink rapidly, but the particles causing the defects do not shrink in the same degree, thus multiple faults are more and more frequent in today's deep sub-micron chips. Scan test patterns are usually calculated to detect single stuck-at faults, and they detect also 'nearly all' multiple faults if at least one of the faults is detectable as a single fault. 'Nearly all' implies that...
In the last decade, the single-threshold IDDQ approach made way for more elaborated techniques like Delta-IDDQ and adaptive IDDQ. Due to increasing background currents, however, also these methods are beginning to have problems to distinguish between good and bad devices. A good evaluation algorithm for IDDQ takes all known information about 'good' and 'bad' parts into account, i.e. it 'knows' how...
The fraction of ICs that pass all production tests but fail in the application is called the defect level. Defect levels depend on the average number of defects per IC, and also on the clustering of these defects. High clustering leads to a higher yield and a lower defect level. This paper compiles the coefficients for defect clustering using research findings from 1970 until 2001. Because recent...
For production test and characterization of DACs, the non-linearity is one of the most important values to be measured. For this end, usually a digital ramp signal is applied at the input of the DAC, its output signal is captured and evaluated. Sometimes the measurement is disturbed by drift of the DC offset or low-frequent noise, originating e.g. from the tester's analog capture instrument or the...
Measuring the sensitivity of a system (e.g. a sensor) is usually done by sequentially applying different input levels and measuring the difference of the output levels. Repeating this procedure several times significantly reduces the effect of slow fluctuations; however these can be removed completely by choosing an optimal sequence of input stimuli. We used the binary thue-morse sequence as a stimulating...
In SoCs (system-on-chip) with mixed-signal cores, both the functional behavior and the production tests should be simulated at top level before tape-out. The use of behavioral models for the analog and mixed-signal cores enables simulation of the whole signal path including the analog inputs or outputs of the mixed-signal cores. Since many SoCs are described in the Verilog HDL (hardware description...
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