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A full-duplex transceiver front-end architecture that employs inverse class-D switching power amplifiers is described. An LC phase-shift network is employed between the receiver port and the antenna port. By proper phasing of the switching devices, the transmitted signal can add constructively at the antenna port while canceling at the receiver port, thereby enabling full-duplex operation. The motivation...
A low-power Weaver image-reject receiver based on 3rd-order signal recursion is demonstrated. The design employs two downconverters and seeks to enhance the dynamic range and gain-bandwidth product per unit power dissipation metric by adopting recursive gain reuse at multiple frequencies. Utilizing an LO at frequency fLO, the downconverter recursively amplifies an RF signal at fRF at 3 distinct frequencies,...
Multi-frequency signal recursion allows for efficient reuse of transconductance in a radio receiver, which helps to reduce power dissipation. An I-Q receiver based on the recursive principle is demonstrated here. The design employs a self-biased load, with chopping at baseband in order to minimize low-frequency in-band flicker noise. The bias setting of the chopper devices is optimized to enhance...
A frequency synthesizer for a 2.4 GHz IEEE 802.15.4/Zigbee compliant transceiver is presented. The VCO has a 15.2% tuning range from 4580-5275 MHz with 135 MHz/V sensitivity. IQ generation for transceiver applications is performed through frequency division at the output of VCO. Frequency dividers employ hybrid circuit styles including CML and TSPC logic. The synthesizer is implemented in TSMC 0.18...
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