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This paper presents a new physics-based method for reliability prediction and modeling of Integrated Circuits (ICs). By implementing transistor degradation mechanisms via differential equations in the transistor compact model, the aging of the circuit can be simulated over (accelerated) time under real conditions. Actually, each transistor in the circuit integrates the voltage, current and temperature...
This paper presents a new physics-based method for reliability prediction and modeling of Integrated Circuits (ICs). By implementing transistor degradation mechanisms via differential equations in the transistor compact model, the aging of the circuit can be simulated over (accelerated) time under real conditions. Actually, each transistor in the circuit integrates the voltage, current and temperature...
Die shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter hot carrier injections (HCI). This failure mechanism causes a performance degradation of digital ICs. The evaluation of timing degradations becomes a must-have to ensure the expected time-to-market and IC lifetime early in the design flow. In this paper, we present a design/verification...
The reliability of InP/GaAsSb/InP DHBTs designed for very high-speed ICs applications is studied after storage accelerated aging tests performed up to 2000 hours at ambient temperatures of 180, 210 and 240°C. The HiCuM model was used for modelling DC electrical characteristics measured during aging tests. The signature of the major degradation mechanism points out an evolution of the emitter access...
In semiconductor industry, designing a SoC is a complex process. Designing reliable SoCs includes study of various configurations involving different operating conditions and considering both hard and soft errors. Designers at higher level of abstraction already have many ways to remove or handle soft errors. This paper aims at analyzing hard errors at functional level. We propose a methodology using...
With the increase in the design complexity of MPSoC architectures, estimating power consumption is very complex and time consuming at lower level of abstraction. We propose a methodology using ArchC named Power-ArchC for a fast high-level estimation of processor power consumption. Power values are obtained by an instruction level power characterization at gate level. The requirements for power evaluation...
In this paper the modeling results of a given InP/InGaAs/InP DHBT technology (0.7 × 7 μm emitter area) have been shown with two advanced compact models, HICUM L0 and Agilent HBT. Shortcomings of these models have been pointed out and their suitability for modeling these high frequency devices has been discussed.
The lifetime of integrated chip tends to decrease more and more with technology scaling. To check if a design is robust, in this paper we present RTME (real time MTTF evaluation), a simulation framework that enables the evaluation of reliability at higher level of abstraction layer. Using the output of RTME, we are able to distinguish the effect of different benchmarks on different blocks of the processor.
The first pulsed solid-state frequency-shifted-feedback laser as polychromatic laser guide star is reported. A Ti:Sa frequency-shifted-feedback (FSF) laser delivering a broad continuous spectrum in order to cover (after frequency mixing) the hyperfine-Doppler width of the 3S1/2 rarr4P3/2 transition at 330 nm is developed. The developed Ti:Sa laser can operate either in cw or pulsed mode. This new...
This paper proposes a multi-agent planning framework. It presents an integral cycle we developed to build feasible multi-agent plans in a dynamic context (i.e. aircraft simulation). This cycle takes into account both functional and computational features of our multi-agent planning framework. From modeling to validation, this cycle allows the management of different constraints (e.g. time, physical...
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