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While compaction of binary test sequences for generic sequential circuits has been widely explored, the compaction of test programs for processor-based systems is still an open area of research. Test program compaction is practically important because there are several scenarios in which Software-based Self-Test (SBST) is adopted, and the size of the test program is often a critical parameter. This...
Transition faults are used for modeling delay defects. A comparison between transition faults and single stuck-at faults indicates that many more transition faults than single stuck-at faults in standard-scan circuits are undetectable. Furthermore, this paper shows that undetectable transition faults in benchmark circuits appear in larger clusters than single stuck-at faults, where a cluster consists...
Test sets that consist of both broadside and skewed-load tests provide improved delay fault coverage for standard-scan circuits. This paper describes a static test compaction procedure for such mixed test sets. The unique feature of the procedure is that it can modify the type of a test (from broadside to skewed-load or from skewed-load to broadside) if this contributes to test compaction. Experimental...
It was recently observed that the methods to generate scan based tests with low switching activity cause about 40% less activity than functional tests. Thus such tests may cause test escapes as they may not adequately stress the circuits under test. In this work we propose a method called Max-Fill to generate high quality partially-functional broadside delay tests. The generated tests are shown to...
Recently a new method called ATE assisted compaction for achieving test response compaction has been proposed. The method relies on testers to achieve additional compaction, without compromising fault coverage, beyond what may already be achieved using on-chip response compactors. The method does not add additional logic or modify the circuit under test or require additional tests and thus can be...
Functional broadside tests are two-pattern scan-based tests that avoid overtesting by ensuring that a circuit traverses only reachable states during the functional clock cycles of a test. On-chip test generation has the added advantage that it reduces test data volume and facilitates at-speed test application. This paper shows that on-chip generation of functional broadside tests can be done using...
3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing...
A test for a delay fault can be considered as covering a transition on one or more lines. A bias in the transition coverage of a delay test set implies that more rising or more falling transitions are covered by the test set. Such a bias is not captured by fault coverage metrics that consider both types of transitions together. We study the bias in the transition coverage of test sets for path delay...
The usefulness of scan tests with multiple fault activation cycles to improve the coverage of transistor stuck-open faults is investigated. A recent work demonstrated that tests with more than one fault activation cycle can detect additional transition delay faults and inline resistance faults when compared to two-pattern tests applied using the broadside or skewed-load methods. We extend this work...
A new method for achieving test response compaction is proposed. The method involves testers to achieve additional compaction, without compromising fault coverage, beyond what may be already achieved using on-chip response compactors. The method does not add additional logic or modify the circuit under test or require additional tests and thus can be used with any design including legacy designs....
Existing diagnostic test generation procedures are output-independent, i.e., they attempt to distinguish faults on any output. We show that an output-dependent approach can facilitate diagnostic test generation and produce smaller diagnostic test sets for stuck-at faults in full-scan circuits. In the proposed output-dependent approach, the outputs of the circuit are considered one at a time. Faults...
Functional broadside tests were defined to address overtesting that may occur with unrestricted scan-based tests. However, the fault coverage achievable by functional broadside tests is lower than the fault coverage achievable by unrestricted scan-based tests. It was observed that skewed-load tests can improve the fault coverage achievable by unrestricted broadside tests. Motivated by these observations,...
Bridging and interconnect open faults are defined using subsets of lines. We study the possibility of identifying input vectors that are effective as test vectors for such faults without enumerating the faults. This process does not require accurate layout information, it can handle very large numbers of faults, and it deals with undetectable faults implicitly. We describe a static test compaction...
Diagnostic ATPG has traditionally been used to generate test patterns that distinguish pairs of modeled faults. In this work, we investigate the use of n-distinguishing test sets, which distinguish pairs of single stuck-at faults n times, to enhance the probability of distinguishing unmodeled defects. The basis for the use of n-distinguishing test sets to enhance defect diagnosis is similar to that...
Transparent-scan provides opportunities for test compaction that do not exist with the conventional test application scheme for scan circuits. However, test compaction can reduce the ability of a transparent-scan sequence to diagnose faults. We describe a static test compaction procedure that reduces the length of a transparent-scan sequence while maintaining its stuck-at fault coverage and the number...
It was shown earlier that simulation of a transition fault under a test may indicate that the fault is detected by the test only if detection conditions referred to as hazard-based detection conditions are considered. The hazard-based detection conditions were applied to fault simulation and test generation for transition faults under scan-based tests. In this case, the increase in fault coverage...
Recent studies have shown that new tests are required for the detection of a large percentage of scan cell internal open faults which are not detected by the existing tests. However, the additional coverage due to the new tests drops significantly when opens with moderate resistances are considered. In this paper we propose to augment earlier test methods to detect internal scan chain opens with a...
Broadside tests are two-pattern scan-based tests for delay faults. One of the complications that occur in relation to the application of broadside tests from an external tester is the need to change the primary input vector applied to the circuit at-speed during the test. We explore a solution to this problem where the second primary input vector of every test is produced on chip. The important features...
We define the notion of a lingering synchronization effect. Such an effect occurs when a primary input cube (an incompletely-specified primary input vector) determines the state of a circuit for several time units after it is applied. Such a primary input cube may prevent certain faults from being detected when it appears in a test sequence. It should therefore be avoided when the goal is to achieve...
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compatible faults based on necessary assignments. It guides the justification and propagation decisions to create patterns that will accommodate most targeted faults. The technique presented achieves close to minimal test pattern...
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