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As multiprocessors scale to unprecedented numbers of cores in order to sustain performance growth, it is vital that these gains are not nullified by high energy consumption from inter-core communication. With recent advances in 3D Integration CMOS technology, the possibility for realizing hybrid photonic-electronic networks-on-chip warrants investigating real application traces on functionally comparable...
A many-core processor design for high-performance systems draws from embedded computing's low-power architectures and design processes, providing a radical alternative to cluster solutions.
The performance of sparse iterative solvers is typically limited by sparse matrix-vector multiplication, which is itself limited by memory system and network performance. As the gap between computation and communication speed continues to widen, these traditional sparse methods will suffer. In this paper we focus on an alternative building block for sparse iterative solvers, the "matrix powers...
A traffic matrix is an |S| times |T| matrix M, where Mij is a non-negative integer encoding the number of packets to be transferred from source i to sink j. Chang et al. (2001) have shown how to efficiently compute an optimum schedule for transferring packets from sources to sinks when the sources and sinks are connected via a rearrangeable fabric such as crossbar. We address the same problem when...
We present the design of a reconfigurable VLSI architecture suitable for multirate LDPC decoding. The basic decoder fabric is a square matrix of processing elements which communicate with each other through an interconnection network. The interconnection network consists of links and switches. The connectivity between processing elements is completely defined by scheduling the interconnection network;...
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