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For the first time, we present good yielding 64 Mb SRAM test-chip with the smallest cell using dual/triple gate oxide process flow in 28 nm node. The low power technology platform continues scaling trend and extends SiON/poly technology beyond 32 nm node with gate density of 2.3times higher than that of 45 nm, and integrates high density (0.127 um2) and low Vccmin (0.155 um2) 6-T SRAM cells, low power...
A 32 nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 muA/mum (n/p) are achieved at Ioff=100 nA/mum, Vdd=1 V, 30 nm physical gate length and 130 nm gate pitch. This technology also provides a high-Vt solution for high-performance low-power applications with its high drive currents of...
For the first time, we present a state-of-the-art 32 nm low power foundry technology integrated with 0.15um2 6-T high density SRAM, low standby transistors, analog/RF functions and Cu/low-k interconnect for mobile SoC applications. To our knowledge, this is the smallest fully functional 2Mb SRAM test-chip for 32nm node. Low power transistors with Lg of 30nm achieve current drive of 700/380 uA/um at...
This paper presents the optimum design and bidirectional motion control of slotless double-side permanent magnet linear synchronous motor (PMLSM) system using the control parameters estimation and discrete system modeling. Here, the optimum design and control boundary are restricted by the base range defined as a maximum permissible operating range of PMLSM system in relation with a required mechanical...
We demonstrate a near-field scanned microwave probe and specific test keys for direct non-contact electrical measurement of low-k dielectric constant and damage after deposition, during trench/via processing, and after metallization. This work successfully defines the dielectric constant and the thickness of the damaged layer in patterned low-k films, and is the first demonstration of a metrology...
We demonstrate that after a fine-tuned ashing process the damage behavior of extra low-k material (ELK, k=2.5) is continued at the surface and the thickness of the damaged layer can be kept under control. Therefore, damaged-free treatment can be achieved by process optimization. Finally, we prove the effectiveness of this treatment by using a novel near-field scanned microwave probe to perform microwave...
This paper deals with the dynamic characteristic analysis and parameter estimation of tubular type moving-magnet linear actuator with Halbach array. Control parameters are estimated by experiments and two-dimensional (2-D) analytical solution, derived in terms of magnetic vector potential and cylindrical coordinate systems. And then, the dynamic simulation algorithm is obtained from the voltage and...
This paper deals with the analysis of high speed machines with diametrically magnetized rotor, accounting for slotting effect. On the basis of a two dimensional (2-D) field solutions derived in terms of magnetic vector potential and polar coordinate systems, this paper predicts open-circuit field, armature reaction field, field on load, torque and back emf. In particular, new magnetization modeling...
This paper investigated various approaches to integrate Cu and extra low-k dielectric (ELK, k=2.5~2.2) for dual damascene fabrication. We demonstrate a trench-first hard mask process flow without k degradation by ash-free process and a novel pore sealing technique. In addition, we have extended this pore sealing concept to a via-first PR mask approach for porous ELK of 2.2. Both optimized hard mask...
A systematic study is performed on tantalum carbide (TaC) metal electrode on HfO2 and HfSiON dielectrics using conventional CMOS process. TaC's effective work function (EWF) is estimated to be 4.28 eV on HfO2 using Vfb~EOT methodology, where both interfacial oxide and high-K film thickness are varied and thus charge effect is corrected successfully. Investigation of the EWF dependence on underlying...
A full Cu damascene metallization process was successfully developed for simultaneous formation of sub-0.18 /spl mu/m RF CMOS passive components including circular spiral inductor and MIM capacitor. High quality factor inductor with Q=18 at 1.2 nH was achieved by applying highly uniform Cu CMP process on polishing microns of Cu. Less than 2% Rs uniformity and 70 nm dishing on 95% density Cu line were...
In this work, the dependency of Cu planarization process upon local metal pattern density over a wide density range for 0.13 /spl mu/m applications has been evaluated using a linear polisher. Results show that the amount of metal dishing and erosion strongly depend on metal density with worse planarization observed for higher metal density. The impact of the planarization result on electrical leakage...
This work investigates the leakage current mechanisms in the Cu damascene structure with a methylsilane-doped low-k chemical vapor deposited (CVD) organosilicate glass (OSG) as the intermetal dielectric (IMD). The leakage between Cu lines was dominated by the Frenkel-Poole emission at higher temperatures and at voltages above 5 V. In the structure using a SiN etching stop layer (ESL), the leakage...
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