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This paper investigated various approaches to integrate Cu and extra low-k dielectric (ELK, k=2.5~2.2) for dual damascene fabrication. We demonstrate a trench-first hard mask process flow without k degradation by ash-free process and a novel pore sealing technique. In addition, we have extended this pore sealing concept to a via-first PR mask approach for porous ELK of 2.2. Both optimized hard mask...
A full Cu damascene metallization process was successfully developed for simultaneous formation of sub-0.18 /spl mu/m RF CMOS passive components including circular spiral inductor and MIM capacitor. High quality factor inductor with Q=18 at 1.2 nH was achieved by applying highly uniform Cu CMP process on polishing microns of Cu. Less than 2% Rs uniformity and 70 nm dishing on 95% density Cu line were...
In this work, the dependency of Cu planarization process upon local metal pattern density over a wide density range for 0.13 /spl mu/m applications has been evaluated using a linear polisher. Results show that the amount of metal dishing and erosion strongly depend on metal density with worse planarization observed for higher metal density. The impact of the planarization result on electrical leakage...
This work investigates the leakage current mechanisms in the Cu damascene structure with a methylsilane-doped low-k chemical vapor deposited (CVD) organosilicate glass (OSG) as the intermetal dielectric (IMD). The leakage between Cu lines was dominated by the Frenkel-Poole emission at higher temperatures and at voltages above 5 V. In the structure using a SiN etching stop layer (ESL), the leakage...
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