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This paper proposes a novel scheme to manage capture power in a pinpoint manner for achieving guaranteed capture power safety, improved small-delay test capability, and minimal test cost impact in at-speed scan test generation. First, switching activity around each long path sensitized by a test vector is checked to characterize it as hot (with excessively-high switching activity), warm (with normal/functional...
Freezing scan cell outputs can block transitions to the combinational components thus reduce shift power. The extra logic introduces area overhead, reduces timing margin and increases power in capture mode. This paper proposes a partial gating flow that calculates instance toggling probability to identify power sensitive cells. The toggling rate reduction tendency is demonstrated to be useful in estimating...
For sub-nanometer designs, testing for small-delay defects (SDDs) is essential to achieve low defect escapes for the manufactured silicon. Existing solutions for testing SDDs are not practical for high-volume production environments due to large pattern count or long compute time, or both. In this paper, we present a production-friendly method that takes the circuit topology into account while generating...
At-speed scan testing has become mandatory due to the extreme CMOS technology scaling. The two main at-speed scan testing schemes are namely Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). As it can be easily implemented, LOC has been widely investigated in the literature in the last few years, especially regarding test power consumption. Conversely, LOS has received much less attention. In this...
As technology scales to 45nm and below, the deviation between predicted path delay using simulation and actual path delay on a manufactured chip increases. Hence, on-chip measurement architectures are now widely used due to their higher accuracy and lower cost compared to using external expensive testers. In this paper, we propose a novel path delay measurement architecture called Enhanced path-based...
Hardware Trojans in integrated circuits and systems have become serious concern to fabless semiconductor industry and government agencies in recent years. Most of the previously proposed Trojan detection methods rely on Trojan activation to either observe a faulty output or measure side-channel signals such as transient current or charge. From the authentication stand point, time to trigger a hardware...
At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs inactive as possible by disabling...
As technology scales to 45 nm and below, process variations will present significant impact on path delay. This trend makes the deviation between simulated path delay and actual path delay in a manufactured chip more significant. In this paper, we propose a new on-chip path delay measurement structure called path-based ring oscillator (Path-RO). The proposed method creates an oscillator from a targeted...
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