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A low-IF fully integrated tuner for DBS satellite TV applications has been realized in 0.13-mum CMOS. A wideband ring oscillator-based frequency synthesizer having a large frequency step was used to downconvert a cluster of channels to a sliding low-IF frequency, while the second downconversion to baseband was performed in the digital domain. Eliminating the inductors and using a small-area oscillator...
Notice of Violation of IEEE Publication Principles"A -85dBc Reference Spurs Quadratude 1-2.5GHz Dual-Path Sampled Loop Filter CMOS PLL with sub-1??rms Phase Noise"by Maxim, A.; Gheorghe, M.;in the 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. San Francisco, CA, 2006After careful and considered review, it has been determined that the above paper is in violation of IEEE's...
A fully integrated 0.13mum CMOS ring-oscillator-based PLL for low-IF single-chip DBS satellite tuner-demodulator IC is presented. A noise-attenuating loop filter reduces the oscillator gain, helping both front-end noise and spur rejection and allowing the on-chip integration of the filter capacitance. The PLL shows <1.5degrms double-sided integrated phase noise, <-60dBc reference spurs, <-50dBc...
A first low-IF fully-integrated tuner for DBS satellite TV applications was realized in 0.13 mum CMOS. A wide bandwidth, ring oscillator integer-N frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a coarsely defined low-IF frequency, while the second down-conversion to base band was performed in the digital domain. Eliminating the oscillator inductors...
Notice of Violation of IEEE Publication Principles??A 9.953-12.5GHz 0.13 ??m Standard CMOS Bondwire LC Oscillator Using a Resistor-Tuned Varactor and a Low-Noise Dual-Regulator??by Maxim, A.; Turinici, C.;in the Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006After careful and considered review, it has been determined that the above paper is in violation of IEEE's...
The first low-IF fully-integrated tuner for DBS satellite TV applications was realized in 0.13 mum CMOS. A wideband ring oscillator based frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a coarsely defined low-IF frequency, while the second down-conversion to baseband was performed in the digital domain. Eliminating the oscillator inductors has...
Notice of Violation of IEEE Publication Principles??A 9.953/10.7/12.5 GHz 0.13 ??m CMOS LC oscillator using capacitor calibration and a VGs/R based low noise regulator??by Maxim, A.in the Proceedings of the 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papers.12-14 June 2005 Page(s):411 - 414After careful and considered review, it has been determined that the above paper...
Notice of Violation of IEEE Publication Principles??A -86dBc reference spurs 1-5GHz 0.13 ??m CMOS PLL using a dual-path sampled loop filter architecture??by Maxim, A.in the Proceedings of the 2005 Symposium on VLSI Circuits, Digest of Technical Papers.16-18 June 2005 Page(s):248 - 251After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication...
Notice of Violation of IEEE Publication Principles"9.953-12.5GHz 0.13??m CMOS LC VCO Using a High Resolution Calibration and a Constant Gain Varactor"by A. Maxim and C. Turinici,in the Proceedings of the IEEE Custom Integrated Circuits Conference, 2005After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.Specifically,...
Notice of Violation of IEEE Publication Principles??A sub-Ips rms jitter 1-5GHz 0.13??m CMOS PLL Using a Passive Feedforward Loop Filter with Noiseless Resistor Multiplication??by Maxim, A.; Gheorghe, M.in the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2005. Digest of Papers.After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication...
Notice of Violation of IEEE Publication Principles??A 2-5GHz low jitter 0.13 ??m CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]??by Maxim, A.in the Proceedings of the IEEE 2004 Custom Integrated Circuits Conference,3-6 Oct. 2004 Page(s): 147 - 150After careful and considered review, it has been determined that the above...
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