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A 0.15 /spl mu/m CMOS technology integrating W/WNx/polysilicon gate electrodes and Ti silicided source/drain diffusions is presented in this paper. Gate electrodes with sheet resistance as low as 1.6 /spl Omega//sq. and Ti silicided source/drain diffusions of 3.6 /spl Omega//sq. are realized. As a result, both the gate RC delay and parasitic source/drain resistance are minimized and high circuit performance...
Degradation process of metal-to-metal antifuses which use thin silicon nitride as dielectric layer under high field stress is studied in detail. Prior to dielectric breakdown, leakage current at stress voltage increases with large and complex fluctuations for any sample. So-called stress-induced leakage current at low voltages in current-voltage characteristics is also observed and it increases as...
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