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The continuous drive to increase the functionality of electronic products in terms of computational efficiency and versatility requires a broad range of interconnect technologies. This paper presents an overview of advanced CMOS Interconnect technology scaling towards the 10 nm node enabling the increase in 2D computational density. Functional versatility is enabled by 3D interconnection technologies...
The filling of microvias with a diameter of 5μm and a depth of 25μm (aspect ratio of 5) by copper electroplating was investigated. Filling experiments were evaluated by analyzing cross-sections of filled vias with scanning electron microscopy and focused ion beam. The fill-up evolution shows a bottom-up mechanism, also known as superfilling mechanism. The evolution of potential with time (chronopotentiometric...
We present two approaches to reduce the process time needed for filling vias of 5 mum diameter and 25 mum depth with copper by electrodeposition. In the first approach, the effect of model additives on the filling of vias with electroplated copper was investigated as well as the influence of the applied current density on the filling process. The variation of the concentration of leveler and accelerator...
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