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An ECL (emitter-coupled-logic) device that achieves 100 K-gate integration with a standard-cell-layout approach is described. A standard-cell CAD (computer-aided-design) architecture enables high-power ECL gate cells and freely placed megacells to be integrated on a chip with fixed-pattern power supply buses. The 3- mu m-thick top (fourth) metal layer is dedicated to the main power buses. Under the...
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