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This paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed...
This paper presents a power-efficient computing platform for hearing aids. The proposed platform composes four heterogeneous processing elements. Each processing element includes one tiny RISC processor and several power-efficient hardwired accelerators. The hardwired accelerators integrate static floating-point and truncated multiplier to improve signal-to-noise ratio and reduce computational complexity...
This paper presents a low-power filter bank design for digital hearing aids, which is compliant with the ANSI S1.11 standard. A multi-rate filtering algorithm and its coefficient design method are proposed, which reduce 94% multiplications. The power dissipation is further reduced by 31% and 35% with switch activity reduction and multi-VDD silicon implementation respectively. The design has been implemented...
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