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Carbon nanotubes (CNTs) show great promise as extensions to silicon CMOS due to their excellent electronic properties and extremely small size. Using a Carbon Nanotube Field Effect Transistor (CNFET) SPICE model, we evaluate circuit-level performance of CNFET technology in the presence of CNT fabrication-related nonidealities and imperfections, and parasitic resistances and capacitances extracted...
1D carbon nanotube FET (CNFET)-based circuits offer 4.6times faster FO4 speed and 12times energy-delay product improvement over 32nm node Si CMOS (including diameter and doping variations), provided circuits can be built that are immune to misaligned and metallic nanotubes. A design technique that guarantees correct logic operation in the presence of misaligned nanotubes is also presented.
In this paper, we describe the development of device models and tools for the design of new transistors such as the carbon nanotube transistor. An HSPICE model for enhancement mode nanotube transistor has been developed. It can be used for design of nanotube transistor circuits as well as to study performance benefits of the new transistor. A model of the carbon nanotube transistor with Schottky barrier...
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