The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The product lifetime (time-in-market) of a high-end embedded SoC (System-on-Chip) can be rather short due to possible design changes, leading to a highly expensive SoC redesign. Most of the SoC redesign are induced by the requirements for function changes of non-programmable ASIC modules. Plenty of the non-programmable ASIC modules are used for bit-wise algorithms. It is thus necessary to offer programmable/flexible...
There are three sets of cryptographic algorithms working on LTE technology and each set based on one core algorithm. In high-end embedded systems, it is necessary to implement the three core algorithms: block cipher AES-128 and stream ciphers SNOW 3G and ZUC, with high performance and low silicon cost. This paper proposes a high throughput ASIP (application-specific instruction-set processor) design...
VLSI (Very Large-Scale Integration) designs for communication coding and decoding should, in general, provide high throughput, achieve low computing latency, occupy low silicon cost, and handle multiple bit manipulation algorithms. Application-Specific Instruction-set Processor (ASIP) is an optimized solution to fulfill all these requirements. This paper presents an ASIP for Cyclic Redundancy Check,...
A high performance table-based architecture implementation for CRC (cyclic redundancy check) algorithms is proposed. The architecture is designed based on a highly parallel CRC algorithm. The algorithm first divides a given message with any length into bytes. Then it performs CRC computation using lookup tables among the divided bytes in parallel. At last, the results are XORed to obtain the CRC value...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.