The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
7nm CMOS FinFET technology featuring EUV lithography, 4th gen. dual Fin and 2nd gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology [1]. EUV lithography, fully applied to MOL contacts and minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity and smaller CD variation. AVT of 6T HD SRAM cell are...
Valve gate locations and open timing for injection molding of an automotive instrument panel is to be determined to minimize the cavity pressure. To achieve design automation for obtaining the solution of this design problem, we first integrated MAPS-3D, a commercial injection molding analysis tool, to PIAnO, a commercial process integration and design optimization (PIDO) tool, using the file parsing...
A novel NOR Flash cell with a build-in 2-bit capability consisting of two physically isolated ONO charge-storage nodes separated by an oxide dielectric in between over the channel region is demonstrated. This memory cell employs the virtual ground array architecture, much like NROM arrays, is sensed with the reverse read scheme. However, comparing to NROM, this novel cell offers a wider Vt window...
The presented theoretical analysis of random telegraph signal (RTS) and 1/f noise data provides consistent interpretation of the measurement results allowing trap characteristics to be extracted and the atomic structure of oxide traps to be identified. We emphasize the critical role of the lattice structural relaxation associated with charge trapping/detrapping, which represents one of the major factors...
Post gate-etch reoxidation in plasma H2/O2 was successfully employed to non-volatile TANOS charge-trap memory devices without any adverse oxidation on the TaN gate-electrode sidewall. Using this plasma reoxidation process showed significant device improvement in the narrow gate retention and endurance characteristics. This improvement is thought to result from gate etch damage repair, and locally...
As CMOS trends continue to scale for future technology nodes, three-dimensional (3D) multi-gate field effect transistors (MugFETs) could be a viable approach. One type of MugGET of particular interest is the FinFET in which a silicon fin is defined on a buried oxide (BOX) layer. The FinFET is attractive because it is compatible with conventional CMOS processing. However, due to the crystal orientation...
We demonstrate best in class performance for MANOS-type charge-trap flash non-volatile memory devices through improved program/erase (P/E), endurance and retention. Band-engineered (BE) tunnel-oxides (TO) and BE-SiNx charge-trap layers are employed to optimize program, erase, and endurance with trade-off in retention. However, for the 1st time we combine BE-TO, BE-SiNx, BE-blocking layer (BE-BL) and...
In this paper, we present a cost-effective 28 nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm2, and, using the ARM Cortex-R4F as a reference, we report achievement of an overall 2.4x area reduction in 28 nm from 45 nm technology. Our high-density SRAM bit-cell (area= 0.120mm2) has a demonstrated...
We present a comprehensive description of the processes contributing to the electron capture/emission by bulk oxide traps, which allows for interpretation of RTS and 1/f noise data and extraction of the trap characteristics. It is shown that the electron capture/emission times could be controlled by the trap structural relaxation (caused by the trapped electrons) rather than by the electron tunneling...
Gate first 0.59 nm EOT HfOx/metal gate stacks for 16 nm node application are demonstrated for the first time. By controlling O during HfOx deposition, ldquozerordquo low-k SiOx interface (ZIL) forms despite a 1020degC activation anneal. This 0.59 nm EOT is a 30% improvement over a state of the art 32 nm HK/MG technology. We compare and demonstrate for the first time the improved scalability of ZIL...
We apply a systematic approach to identify a high-k/metal gate stack degradation mechanism. Our results demonstrate that the SiO2 interfacial layer controls the overall degradation and breakdown of the high-k gate stacks stressed in inversion. Defects contributing to the gate stack degradation are associated with the high-k/metal-induced oxygen vacancies in the interfacial layer.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.