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An on-chip Frequency-Selective-Surface (FSS) integrated with a Proportional-to-Absolute-Temperature (PTAT) circuit for detecting infrared wave in CMOS process is presented. The slot-type FSSs with different slot length reveal different transmission properties. The power absorbed by the chip is analyzed by electromagnetic and thermal simulation software. The measurement results at 28.3 THz show good...
A high-efficiency stacked-film infrared absorber comprising a Jerusalem-cross slot frequency-selective surface (FSS) and Si-based dielectric layers fabricated in foundry CMOS process is proposed. Simulation shows that integration of proposed FSSs with dielectric layers can improve the absorption of the dielectric layers in infrared. A temperature sensing circuit is integrated in CMOS chip to measure...
With the rapid scaling down of CMOS manufacturing technology, the reduction in leakage consumption has become an important concern in low power and high performance applications for nano-scale CMOS processes. This paper presents a MTCMOS (multi-threshold CMOS) power-gating scheme for single-phase adiabatic circuits, which minimizes leakage dissipations during sleep mode. The 8-bit full adder based...
This paper presents a fully monolithic approach to the design and fabrication of THz CMOS image sensor operating at 28.3 THz using the mass-producible 0.18-μm 1P6M CMOS foundry. The CMOS sensor consists of antenna-coupled transducer, linearly transforming the intercepted THz (terahertz) electromagnetic energy into voltage representation in the region of interest. The THz image sensor adopts PTAT (Proportional...
This paper presents the measured results of the distributed thermal image of a 28.3 THz CMOS thermal detector of area 65 um * 45 um, consisting of antenna, thermal-coupling and thermal sensing circuit elements integrated monolithically. In contrast to the conventional THz thermal detectors, the proposed detector design shows subtle temperature distribution profile of the CMOS detector, leading to...
This paper presents an adiabatic tree multiplier based on modified Booth algorithm, which operates in a single-phase power-clock. All circuits are realized using improved CAL (clocked adiabatic logic) circuits with TSMC 0.18 mum CMOS process. The proposed single-phase adiabatic booth encoder attains energy savings of 82% at 50 MHz and 70% at 300 MHz, compared with its CMOS counterpart. The single-phase...
This paper presents a power-gating scheme for CAL (clocked adiabatic logic) circuits to reduce energy loss during idle state. A transmission gate is used as the power-gating switch. It is inserted between the single-phase power-clock and virtual power-clocks to detach power-gated CAL logic blocks during idle periods. The 8-bit full adders based on the CAL circuits are used to verify the proposed power-gating...
A low power pulsed edge-triggered latch based on the static edge-triggered latch (ETL) is presented for survivor memory (SMU) unit of Viterbi decoder for low power high speed wireless local area network (WLAN) applications. By reducing clock loading and transistor number, the proposed low swing static ETL has less clock loading, smaller cell area and power-delay product compared to traditional master-slave...
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