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RDL process becomes more and more important with through Si interposer (TSI) application in 3D packaging. RDL line/space needs to be shrinking with the increasing of device density. We had been developed low temperature (LT) damascene process for the RDL formation in 3D interposer integration. The sample failed at thermal reliability test. High temperature (HT) RDL was developed and demonstrated after...
Through-silicon via (TSV) is an important enabler for future 3-D integration of integrated circuits. TSV typically contains a high-aspect-ratio metal via embedded in silicon and electrically isolated from the silicon by a layer of dielectric liner hence forming a metal-oxide-semiconductor structure. The parasitic capacitance introduced by TSV must be kept as low as possible for low latency signal...
3D integration by TSV approach is a very hot topic now as an enabling technology for 3D wafer-level packaging and 3D IC. Re-distribution layer (RDL) process becomes more critical on high volume Cu (TSV) wafer because of Cu thermal stress effect. Fine pitch low temperature RDL is required in 3D packaging and 3D IC integration. We develop fine pitch (5μm space/5μm width) single and dual damascene processes...
3D integration by TSV approach is a very hot topic now as an enabling technology for 3D wafer-level packaging and 3D IC. Re-distribution layer (RDL) process becomes more critical on high volume Cu (TSV) wafer because of Cu thermal stress effect. Fine pitch low temperature RDL is required in 3D packaging and 3D IC integration. We develop fine pitch (5µm space/5µm width) single and dual damascene processes...
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