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The paper introduces a new low power, high density double edge triggered, (DET) flip-flop. The proposed DET flip-flop is implemented using lesser number of transistors as compared to other state of the art double edge triggered flip-flops designs. Simulation at 250MHz frequency using 180nm/1.8V CMOS technology with BSIM 3v3 parameters, the proposed design shows an improvement of upto 58.63%, 55.7%...
In this paper, low voltage cascode current mirror based on bulk-driven MOSFET (operating in linear region) and floating-gate MOSFET are presented. The proposed circuits are simulated using SPICE for 0.25 mum CMOS technology and their results are compared with that of conventional cascode current mirror.
This paper proposes a novel floating gate MOSFET (FGMOS) based voltage-controlled grounded resistor (VCGR). The FGMOS is used to cancel the nonlinearity term present in the drain current equation of MOSFET operating in ohmic region. The implementation of nth order tunable high-pass filter using the proposed VCGR is also suggested. The proposed VCGR is simple, compact, accurate, and with low power...
The work thus presents GEWE-RC MOSFET as a potential candidate for high performance RF applications and achieves fi of 48.6 GHz which is a 31.7 % and 48.5 % improvement as compared to the RC and bulk respectively, at Vgs = 1.0 V, for same set of design parameters, owing to the improved gate controllability and reduced parasitic capacitances. Moreover,intrinsic delay and high gains pertained by GEWE-RC...
In this paper, the linearity performance of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET is investigated using ATLAS device simulator, based on the concept of intercept point. Further, the impact of various technological parameter variations, such as gate length (LG), negative junction depth (NJD), screening metal gate workfunction (PhiM2) and substrate doping (NA) on the...
This paper focuses on the TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET as a solution to CMOS technology for high performance analog applications in terms of speed-to-power dissipation, device efficiency and hot electron injected gate current design parameters. Moreover, the paper also discusses the effect of gate stack architecture and various design...
A 1.8GHz wideband fractional-N synthesizer achieves the phase noise of an integer-N PLL using a noise-cancellation DAC calibrated with an adaptive LMS spur correlation technique. It exhibits in-band and integrated phase noises of -98dBc/Hz and 0.8deg, respectively. The chip in 0.18mum CMOS occupies 2mm2, and consumes 29mW at 1.8V
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