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The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were fabricated using 0.18-mum CMOS technology. The first and second stages of the driver consisted of a single inverter and m inverters, respectively, and the register array stage was constructed with N delay flip-flops (D-FFs)...
A new DC/DC level converter has been developed for use in high-speed, low-power circuits. The level converter can increase the DC voltage which is supplied to an active-load circuit on request, or supply a minimal DC voltage to a load circuit in the stand-by mode. 32-word register files and 512-bit cache SRAMs were developed using 0.25-µm HEMT technology to examine the effectiveness of the DC/DC level...
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