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Multi-Pixel Photon Counter (MPPC) is solid-state photon counting device consisting of a Geiger-mode APD and quenching resistor at the most basic level. To improve the total fill factor of a MPPC array, we have adopted new technologies such as metal quenching resistors (MQR), through-silicon vias (TSV), stealth dicing (SD), and highly accurate assembly techniques. We have confirmed the reliability...
In this paper, we propose a musical-noise-controllable algorithm for array signal processing with the aim for high-performance and high-quality noise reduction. Recently, many methods of integrating linear microphone array signal processing and nonlinear signal processing for noise reduction have been studied, but these methods often suffer from the problem of musical noise. In the proposed algorithm,...
In this paper, we propose a new blind speech extraction microphone array combining an independent component analysis (ICA)-based noise estimator and nonlinear signal processing for achieving high-quality speech enhancement. The proposed method consists of three parts, namely, the ICA-based noise estimator for a robust target cancellation, channel-wise spectral subtraction (chSS), and post-beamforming...
This paper evaluates four designs of XOR employing our previously presented two-phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. 2PASCL XOR, which demonstrates the lowest power dissipation, is used for the 4 × 4-bit array 2PASCL multiplier. From our simulation results, at transition frequencies of 1 to 100 MHz, the 4 × 4-bit array 2PASCL multiplier shows a maximum of 55% reduction...
We demonstrate a highly functional Si-nanodot-array device that has three input gates and two output terminals. The device was fabricated on an SOI wafer using Si MOS processes. We confirmed that a single device can operate as both a half adder and a full adder when we carefully select the operation voltages.
A 1-kb memory-cell array composed of single-electron shut-off (SESO) cells was fabricated with the 90-nm logic process for the first time. It features a 0.1-FIT/Mb soft error, 100-MHz random cycle, and 100-ms retention. In addition to a logic-compatible cell structure and a write-data caching scheme, a backup latch circuit with SESO transistors for logic application was also proposed.
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