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This paper presents a novel application-dependent interconnect testing scheme for Xilinx FPGAs. In this scheme, the interconnects in FPGAs' application configuration (AC) are decomposed into line branches, and the targeted line branches are partitioned into multiple subsets so that the CLBs' test configurations required to test the line branches in each subset are compatible. Multiple test configurations...
In this paper, a 10-bit 50-MS/s analog-to-digital converter (ADC) is presented. A power consumption of 10.6 mW is designed by using low power gain-boosted OP-Amp and dynamic comparator. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This circuit is designed in a SMIC 1.2-V 0.13-um CMOS technology. The results show that the proposed Nyquist rate ADC provides a potential...
Sleep transistor (ST) insertion is a valuable leakage reduction technique in circuit standby mode. Fine-grain sleep transistor insertion (FGSTI) makes it easier to guarantee circuit functionality and improve circuit noise margins. In this paper, we introduce a novel two-phase FGSTI technique which consists of ST placement and ST sizing. These two phases are formally modeled using mixed integer linear...
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