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Due to inappropriate assignment of bump pads or improper placement of I/O buffers, the configured delays of I/O signals may not satisfy the timing requirement inside die core. In this paper, the problem of timing-constrained I/O buffer placement in an area-IO flip-chip design is firstly formulated. Furthermore, an efficient two-phase approach is proposed to place I/O buffers onto feasible buffer locations...
The concept of merging some 1-bit flip-flops into a multi-bit flip-flop is applied to reduce dynamic clock power and decrease the total flip-flop area in a synchronous design. To acquire these advantages, the design must be guaranteed to satisfy certain physical constraints in the merging process. In this paper, given a set of 1-bit flip-flops with the input and output timing constraints, the area...
With the use of non-tree topology in signal nets, the delay issue in non-tree topologies has become an important problem. In this paper, based on the transformation-based timing analysis for a non-tree interconnection, an iterative wire-sizing approach is proposed to assign feasible widths onto the wire segments to minimize the timing delay in the critical path for a non-tree interconnection under...
As the clock frequency increases, signal propagation delays on PCBs are requested to meet the timing specifications with very high accuracy. Generally speaking, the length controllability of a net decides the routing delay of the net. If a routing result has the higher length controllability, the routing delay will be obtained with higher accuracy. In this paper, given a start terminal, S, and a target...
Based on the assumption of a single wiring open in a signal net, it is known that the non-tree topology for a signal net has no adjacent loop. In this paper, based on RC non-tree transformation in Elmore delay model, an optimal algorithm for timing analysis is firstly proposed to compute the timing delays of all the reference nodes in a non-tree topology. Compared with the SPICE tool, the experimental...
Designs with non-tree consideration have been proven to improve the yield and reliability in modern chips. In this paper, an efficient three-phase approach for transformation-based timing analysis is proposed to transform a cyclic graph into an acyclic graph by using the node-splitting operation and compute the delay of the transformed tree-based circuit in an Elmore delay model. Compared with the...
Given a set of connecting nodes in a signal net with a set of obstacles on different layers for 3D ICs, based on the refinement of minimum routing region and the concept of hidden Steiner-point assignment on the same layer or different layers, a merging-based approach is proposed to construct a timing-driven 3D rectilinear Steiner tree with obstacle avoidance. Compared with a spanning-tree-based approach,...
In this paper, based on the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias. For the Poisson yield model in redundant via insertion, the experimental results show that our proposed...
Given a set of connecting nodes in a signal net on different layers for 3D ICs, based on the concept of hidden Steiner-point assignment on the same layer or different layers, a merging-based approach is proposed to construct a timing-driven 3D rectilinear Steiner tree. Compared with a spanning-tree-based approach, the experimental results show that our proposed approach has 9.7%~16% improvement in...
Given a circuit netlist, based on the slack analysis in the netlist, the optimal voltage in a maximum slack-sharing cluster(MSC) can be obtained to maintain the performance of the netlist. Furthermore, according to the optimal voltages of all the MSCs and the constraints for multiple-voltage assignment, an efficient assignment approach is proposed to assign multiple voltages onto the given circuit...
Given a routing panel, the routability-driven ordering and location constraints can be firstly set according to the pin positions of all the wire segments in the panel Based on routability-driven ordering and location constraints in the panel, an ASAP-based scheduling approach with efficient space insertion is further proposed to reduce total coupling capacitance for routability-driven track routing...
In this paper, given a set of connecting nodes in a signal net, based on the result of optimal wire width and buffer insertion in a wire segment (Yan, 2006) and the concept of sharing-buffer insertion and hidden Steiner-point assignment, an effective tree construction approach is proposed to construct a timing-driven rectilinear Steiner tree with wire sizing, buffer insertion and obstacle avoidance...
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