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Since thermal responses of the drive current in recent 3D FinFET and conventional planar transistors are different, addressing performance and reliability in advanced VLSI circuits must be reconsidered. This study investigates temperature effects on two of the most problematic reliability issues in modern logic circuits, namely Bias Temperature Instability (BTI) and soft errors. In particular, we...
As technology nodes are gradually shrinking, adding soft error tolerant features to logic circuits is becoming a challenging task that requires careful consideration. Careless use of sizing technique may even worsen immunity to soft errors for circuits with very small nodes. This paper investigates limitations of conventional sizing methods and introduces new techniques for mitigating soft errors...
Dealing with soft errors due to particle strikes is the next major challenge in implementing digital systems. This study thoroughly investigates the effect of device size on circuit soft error rate and identifies methods to reduce soft error rate in combinational circuits. In particular, we propose three novel methods that upsize only selected gates and /or transistor networks. In order to obtain...
As technology nodes are being scaled down, soft errors induced by particle strikes are becoming a troublesome reliability issue in logic circuits. Various sizing techniques commonly used to reduce soft error rate in the past are expensive in terms of area, performance, and energy consumption. These methods require changes to adapt to sub-micron technologies. This study introduces two novel sizing...
Negative bias temperature instability (NBTI) has been identified as a major and critical reliability issue for PMOS devices in nano-scale designs. It manifests as a negative threshold voltage shift, thereby degrading the performance of the PMOS devices over the lifetime of a circuit. In order to determine the quantitative impact of this phenomenon an accurate and tractable model is needed. In this...
This article describes an efficient approach to the implementation of bit-serial lattice wave digital filters based on field programmable gate array (FPGA). In this paper, a time schedule of all of the bit-serial two-port adaptors is presented as a bridge between conception and completion. Finally, with the satisfying frequency response, the filter is successfully tested by both computer simulation...
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