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Marine CSEM (controlled source electromagnetic method) Acquisition Station needs to accurate observe two magnetic field components (Hx, Hy) and three electric field components (Ex, Ey, Ez). In this paper, a series of calibrations are made for the low noise chopper amplifier, which is used in the electric field signal acquisition hardware circuit. The calibration signal generation and the calibration...
Many current source models (CSMs) have been proposed for the gate-level circuit analysis and timing analysis for sub-90-nm CMOS designs during the past decade. However, most of them may suffer from large delay errors for multiple-stages of combinational logic gates. This paper presents an extended CSM which can provide high accuracy in both single-stage and multiple-stage combinational logic gates...
Automatic human gesture recognition from camera images is an interesting topic for developing intelligent vision systems. In this paper, we propose a convolution neural network (CNN) method to recognize hand gestures of human task activities from a camera image. To achieve the robustness performance, the skin model and the calibration of hand position and orientation are applied to obtain the training...
This paper presents a CMOS on-chip transformer characterization for line driver applications of digital transmission using differential signals. The central-tap structure for the secondary coil is designed carefully to ensure the signal integrity after converting the signal into differential format, while the broadside-coupled configuration for the coils is utilized to enhance the transformer coupling...
This paper presents design and test of a planar transformer using 0.18 µm CMOS technology with BALUN applications. To enhance the transformer coupling coefficient of the primary/secondary coil, the broadside-coupled structure is adapted while the circuit size is also minimized in chip area of 190 µm × 190 µm. The measured results based on the differential-/common-mode thru-reflect-line (TRL) calibration...
This paper presents a transmitter and receiver phased array chipset fabricated in a 0.18µm SiGe BiCMOS process with ƒT / ƒMAX of 240/270GHz. Each chip comprises four phased array elements with distributed calibration memory and calibrated direct up and down-conversion mixer chain. Both transmitter and receiver arrays operate from 1.5V and 2.5V power supplies and consume 1W each. Each receive channel...
A 14-b 150MS/s current-steering DAC with background calibration technique is demonstrated. Digital background calibration loop trims the static performance less than plusmn 0.55 LSB. The DAC achieves the spurious free dynamic range (SFDR) of 81dB at 1.6MHz and 67dB at 48.75MHz for sampling rate of 150MS/s. The DAC is implemented in a 0.35 mum CMOS process and active area is a 2.4times1.2 mm2
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