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Hold-time faults are gaining attention in modern technologies because of process variation, power supply noise, and etc. A path-based hold-time fault model is proposed to cover short paths to and from every flip-flop. In addition, the number of faults is linear to the number of flip-flops in the circuit. Two-timeframe circuit models are proposed for ATPG and fault simulation. We show that traditional...
This paper proposes a fractional-N digital phase-locked loop (DPLL) architecture with feedforward multi-tone spur cancellation scheme. The proposed cancellation loop is capable of suppressing both internal spur, i.e., fractional-N spur, and externally coupled spur from input paths. It can be further extended for multi-stage operation for mitigating multiple spur sources. Both theoretical analysis...
A low-spur PLL is desirable for many applications since it avoides mixing unwanted blocker signals, prevents emission mask violations or minimizes jitter in the clock source. Internal spurs result from the nature of PLL operation and include reference spurs and fractional spurs when the PLL is operated in fractional-N mode. External spurs are caused by nearby disturbances, such as coupling from other...
A dual-rate hybrid DAC is proposed in [1] that shows a path toward high speed/linearity in scaled technology. In this hybrid architecture, the resolution of the DAC is achieved through an oversampled LSB path, while its output power is mostly delivered by a Nyquist MSB path, resulting in a reduced number of current-steering cells and relaxed amplitude-matching requirement via digital pre-distortion...
In recent past, the rapid developing of mobile internet inspires the widespread use of WiFi (IEEE 802.11) technology. In WiFi, the access control of a terminal to the router remains a significant challenge because the PIN (password) and MAC address are easy to guess and forge. In this paper, we present FastID - a practical system that identifies WiFi terminals in real-time by fingerprinting their...
A new type of low power decoding circuit for asynchronous sigma delta modulators is presented. The circuit implements a special coarse-fine time-to-digital converter to quantize the square wave produced by asynchronous sigma delta modulators, and converts the duty cycle to a digital output. The time-to-digital converter operates asynchronously by utilizing vernier delay lines. The purpose of this...
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