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Based on the test structures and silicon measurement data done at 40nm technology, we analyze the impact of varying length between the contacted active-area and gate (S) on the performance of NMOS dogbone devices, such as saturation drain current (Idsat), threshold voltage (Vth), and leakage current (Ioff). The experiments show that as the length between the contacted active area and gate (S) is increased...
In this paper, a monolithic V-band low noise amplifier (LNA) is presented by using 0.15μm gate length GaAs/InGaAs/AlGaAs pseudomorphic HEMT technology. The LNA is consisted by 4 stages 4×30μm gate width transistors. The total circuit achieves 2.2–2.7 dB noise figure with more than 16dB associate gain from 57GHz to 66GHz, and the saturation output power reaches 15dBm. The chip area is 2.1mm×1.5mm.
NCL X circuit is a very efficient way to implement the QDI circuit, which can get all the advantages of the asynchronous circuit, especially the average performance. But the NCL_X circuits suffer from its huge area overhead. To solve this problem, a method for optimizing the complete detection network in the NCL_X circuit has been introduced in this paper. Using this method can dramatically reduced...
Timed asynchronous circuits are efficient in performance and power consumption. Traditional performance analysis method can not analyze timed circuits efficiently. In this paper, we model timed circuits using timed Petri net and digraph. We studied the mean cycle time of timed Petri net model. The upper bound and lower bound of mean cycle time were given. Then we proposed an algorithm for timed circuits...
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