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A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital converter (ADC) embedded in a system-on-chip (SoC). Digital signal processing (DSP) plays critical roles to assist analog circuits in providing functionalities...
Today's multicore processors and complex multimedia SoCs incorporate power management techniques such as dynamic frequency scaling (DFS), which dynamically changes operating frequencies, and dynamic core-count scaling (DCCS), which rapidly power cycles the cores between active and idle states. For digital clocking in such SoCs, the PLL needs to support rapid frequency change and fast locking, both...
We present a direct sampling full-band capture receiver for cable and digital TV applications. It consists of a 28nm CMOS ADC-based direct sampling receiver and a 0.18um BiCMOS LNA. It is capable of receiving 158 channels from 48MHz to 1000MHz simultaneously, achieving up to 10Gb/s data throughput, while exceeding DOCSIS requirements. The CMOS receiver occupies 1mm2 area while consuming 300mW. The...
An All-Digital PLL (ADPLL) in 28 nm CMOS is designed to generate low noise clocks for high-speed ADCs. A high-resolution (< 1 ps), short-span (6 ps) Time-to-Digital Converter (TDC) is implemented to improve the phase noise with little cost of power and area. This ADPLL has < 230 fs RMS jitter at 50 MHz reference frequency, with 8.5 mW power from 1.8V supply and an area of 0.07 mm2.
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