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The SPARC64 V microprocessor is designed for use in high-reliability, large-scale unix servers. In addition to implementing ECC for large SRAM arrays, the SPARC64 V microprocessor incorporates error detection and recovery mechanisms for processor logic circuits and smaller SRAM arrays. The effectiveness of these error recovery mechanisms was validated via accelerated neutron testing of Fujitsupsilas...
A 170GB/S crossbar for a multiprocessor server is realized with 10 LSIs. High density and low power are achieved with a 1.333 Gb/s single-ended signal transmission, a driver using pre-emphasis, and a receiver using a data-synchronous scheme. The total bandwidth of the address crossbar LSI is 1.23Tb/s with 704 drivers and 352 receivers
Current high-end microprocessor designs focus on increasing instruction parallelism and clock frequency at the expense of power dissipation. This paper presents a case study of a different direction, a chip multiprocessor (CMP) with a smaller processor core than a baseline high-end 130-nm 64-bit SPARC server uniprocessor. We demonstrate that the size of the baseline processor core can be reduced by...
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