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Electrically active defects in silicon-based epitaxial layers on silicon substrates have been studied by Deep-Level Transient Spectroscopy (DLTS). Several aspects have been investigated, like, the impact of the pre-epi cleaning conditions and the effect of a post-deposition anneal on the deep-level properties. It is shown that the pre-cleaning thermal budget has a strong influence on the defects at...
In this work, the impact of Negative Bias Temperature Instability (NBTI) and Channel Hot Carrier (CHC) stresses on different regions along the channel of the MOSFET gate dielectric is analyzed at the nanoscale with Conductive Atomic Force Microscope (CAFM). In particular, it is demonstrated that, while the BTI degradation is homogeneous, the CHC stress degradation is higher close to source (S) and...
This paper discusses the impact of strain on the low-frequency (LF) noise performance of deep submicrometer MOSFETs. The effect of different strain-engineering approaches, i.e., global, using strained silicon (sSi) substrates on thin SiGe strain-relaxed buffer (SRB) layers or local, relying on recessed SiGe source/drain (S/D) regions or nitride stressors is described. In the case of sSi nMOSFETs,...
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