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On-chip routing elements are extensively used in complex NoC designs. Faulty operation of such elements due to crosstalk faults or soft errors can severely affect a device's functionality and performance. This article investigates the application of different hardware- and software-based approaches to improving these elements' dependability, and discusses the advantages and drawbacks of these approaches...
This work presents a fault-tolerant version of the mass-produced 8-bit microprocessor M68HC11. It is able to tolerate single event transients (SETs) and single event upsets (SEUs). Based on triple modular redundancy (TMR) and time redundancy (TR) fault tolerance techniques, a protection scheme was implemented at high level in the sensitive areas of the microprocessor by using only standard gates in...
This work intends to evaluate the effect of a single event upsets (SEUs) and crosstalk faults in a NoC router architecture by developing a fault injection mechanism, allowing an accurate analysis of the impact of SEU and crosstalk over the router service. Results show that such faults may affect the router behavior, causing loss of packets, errors in packet information or even compromising the router...
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