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This paper presents an innovative method that allows the use of dynamic partial reconfiguration combined with triple modular redundancy (TMR) in SRAM-based FPGAs fault-tolerant designs. The method combines large grain TMR with special voters capable of signalizing the faulty module and check point states that allow the sequential synchronization of the recovered module with the Xilinx TMR (XTMR) approach...
Test sequences for interconnection testing in network-on-chips (NoC) are usually small. However, to ensure a good fault coverage, the sequence is usually re-applied for a number of paths configurations in the network. In this paper we first analyze the test configuration time required for a functional test strategy devised for mesh NoCs and we show that this time, specially for BIST-based solutions,...
On-chip routing elements are extensively used in complex NoC designs. Faulty operation of such elements due to crosstalk faults or soft errors can severely affect a device's functionality and performance. This article investigates the application of different hardware- and software-based approaches to improving these elements' dependability, and discusses the advantages and drawbacks of these approaches...
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