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This paper presents a wide-band fractional-N frequency synthesizer for multi-standard cellular and short-range wireless communication receivers. The synthesizer covers the frequency band from 1.8 to 6 GHz and supports the standards of DCS1800, WCDMA, TD-SCDMA, WLAN802.11 a/b/g and Bluetooth. Architecture design and frequency planning are carefully performed to tradeoff wide frequency range and power...
This paper presents a Sigma-Delta fractional-N frequency synthesizer for multi-standard receiver. The synthesizer's output range is 1.8~5.8GHz and covers the standards of DCS1800, WCDMA, TD-SCDMA, WLAN802. Ha/b/g and Bluetooth. Frequency planning is elaborately done to make sure the synthesizer meets specifications of standards mentioned above. QVCO with a proposed phase shifter is shown to have better...
A fully integrated voltage-controlled oscillator (VCO) for IEEE 802.11a WLAN transceivers is proposed and implemented in 0.18 μm CMOS technology with 1.8 V supply voltage. The VCO core adopts the topology of complementary cross-coupled differential inductance-capacitance (LC) tank. The VCO operates from 4.56 to 4.77 GHz with the varactor control voltage (Vtune) changing from 0.3 to 1.5 V and has a...
A low power pulsed edge-triggered latch based on the static edge-triggered latch (ETL) is presented for survivor memory (SMU) unit of Viterbi decoder for low power high speed wireless local area network (WLAN) applications. By reducing clock loading and transistor number, the proposed low swing static ETL has less clock loading, smaller cell area and power-delay product compared to traditional master-slave...
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