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This paper presents a high-gain on-chip antenna implemented in standard Si technology for millimeter-wave applications. A cubic dielectric resonator is mounted upon a ‘microstrip’ form circular patch antenna. Different from other works, a very thin SiO2 layer which is of about 4µm thick is used, and the whole structure is rather simple, which means that it can be easily fabricated and scaled. The...
This paper presents a fast switching frequency synthesizer for a Mode-1 MB-OFDM UWB system. The proposed architecture with a new frequency plan is designed to simplify the synthesizer implementation for optimizing the system power consumption and sideband rejection ratio. This frequency generator consists of a single phase-lock-loop (PLL), a 12-phase coupled ring oscillator, tri-mode divider-by-2...
The Digitally Controlled Potentiometers (DCP) is a new type of electronic device with great developing foreground, which can replace the traditional mechanical potentiometer in many fields. The programmable gain amplifier, programmable filter and others programmable analogy devices can be built using SCM and DCP through programming. Thereby it is realizable to “Set the analogy device onto the bus”...
An RF Transmitter front-end implemented in 0.18 μm CMOS for WiMedia MB-OFDM UWB is presented in the paper, which consists of a V-I converter, an up modulator, a Differential to Single (D2S) converter, a PA and the divided by 2 divider for the LO carrier generation. The post simulation shows the maximum transmitter linear output power level of -2 dBm (3.1-4.8 GHz band) with 6 dB power control range,...
In this paper, a fully integrated CMOS UWB transmitter is presented. The transmitter consists of a band-notched UWB antenna and a transmitter IC which integrates a pulse generator, a gating signal generator and driver amplifiers. The drive amplifier employs a 2-stage amplifier-a class-E amplifier and a class-A amplifier with switch control, to significantly reduce power consumption. Fabricated using...
A low power pulsed edge-triggered latch based on the static edge-triggered latch (ETL) is presented for survivor memory (SMU) unit of Viterbi decoder for low power high speed wireless local area network (WLAN) applications. By reducing clock loading and transistor number, the proposed low swing static ETL has less clock loading, smaller cell area and power-delay product compared to traditional master-slave...
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