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We report a FPGA-hardware implementation of a novel Hough-transform (HT) architecture. A DE4 platform with a Stratix-IV FPGA device has been applied to synthesize a complete prototype system. Due to parallelization of the voting procedure, XGA videos can be processed with a frame delay of 5.4 ms at an operating frequency of 200MHz. System suitability for detecting road lanes in automotive applications...
With the development of VLBI technology, the correlator system of observation station is constantly upgrading, so as to adapt to new data format and higher processing speed. Now the conversion of data format from Mark 5B to VDIF has been built by the researchers around the world. Once completed, it will be conducive to VLBI international collaboration. Hence it is very meaningful to study the VDIF...
Current technology scaling is leading to increasingly fragile components, making hardware reliability a primary design consideration. Recently researchers have proposed low-cost reliability solutions that detect hardware faults through software-level symptom monitoring. SWAT (SoftWare Anomaly Treatment), one such solution, demonstrated with microarchitecture-level simulations that symptom-based solutions...
This paper presents a high-performance design of dc-dc switching power converter system, which can deliver a regulated 0–50V and 0–15A output. The full-bridge phase-shift converter is realized with zero voltage switching and UCC3895 IC to achieve higher efficiency and pulse width modulation. For wide range of adjustable voltage output control, a PI gain-scheduling control scheme is proposed and implemented...
A novel architecture of the configurable Distributed Random Access Memory (RAM) logic based on Look-Up Tables (LUTs) in the Logic Block (LB) is proposed and implemented in a tile-based FPGA manufactured with a 0.5μm SOI-CMOS logic process. The Distributed RAM can be configured in two modes: Single-Port RAM and Dual-Port RAM. Due to its resource abundance and low latency the Distributed RAM can complement...
This paper addresses the design of the mapping tool used for the FPGA application implementation in our SRAM-based FPGAs fabricated in a 0.5 micron SOI-CMOS process. Comparing with the existing mapping tools from academia, we propose several techniques of packing and clustering to improve the technology mapping. The proposed algorithms provide a closer matching of the user logic netlist with the underlining...
In this paper, we propose a methodology of the automated bitstream generation for conducting high-testability FPGA tests. In order to study the efficiency of our solution we will explore our methodology in the test of an SOI-based FPGA. We use a semi-automated approach of the bitstream generation for ease of test vector design with high functionality and fault coverage. The methodology from this research...
A novel Boundary-Scan circuit compatible with IEEE 1149.1 standard and designed for our SOI-Based FPGA is presented in this paper. The new Boundary-Scan circuit serves the test of FPGA at the chip as well as board level and the added features facilitate the configuration and verification functions of FPGA. The Boundary-Scan circuit in this paper has been implemented in an SRAM-Based FPGA fabricated...
A large and sudden current called surge current is always induced due to the momentary supply current through a low resistance path to ground when filed programmable gate array (FPGA) power on. This surge current will request the power supply of FPGA to source more current to meet this instantaneous demand or complicate the power management system of FPGA in order to succeed in powering up FPGA. Therefore,...
A novel logic block circuit consisting of two multi-mode logic cells is proposed for the design of a tile-based FPGA fabricated with a 0.5μm SOI-CMOS logic process. Each logic cell contains two 3-LUTs. The proposed 3-LUT based logic cell circuit increases logic density by about 12% compared with a traditional 4-LUT implementation. The logic block can be used in two functional modes: LUT mode and Distributed...
The exploitation of dynamic and partial hardware reconfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial...
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