The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A novel low temperature wafer-level Cu-Cu bonding method using Ag nanoparticles (NP) was proposed and realized in this paper. A bonding structure consisted of Cu bonding pads, TiW barrier/adhesive layer was firstly fabricated on the silicon wafer. Ag NPs were then deposited by physical vapor deposition (PVD) on Cu pads. The morphology of Ag NPs annealed at different temperature was studied. Bonding...
The density of the packaging is recently increasing for miniaturization of the electronic system, especially 3D SiP (System in Package). Interposer is a significant research area for 3D packaging which always uses three kinds of materials including silicon, glass and organic. Currently, there are a lot of researches about silicon interposer because the CTE (Coefficient Thermal Expansion) and process...
3D Integration is a good solution for extending Moore's momentum in the next decennium. Through Silicon Via (TSV) is an alternative interconnect technology for higher performance system integration with vertical stacking of chips in package. Due to high demands of chip miniaturization, small diameter TSV with high aspect ratio has become particularly important. This paper focuses on Cu electroplating...
Copper chemical mechanical polishing (CMP) and wafer thinning technologies have been challenges for Through Silicon Via (TSV) interconnect in recent years. In this work, copper CMP slurry and process and wafer level thinning with temporary bonding were studied in detail. The concentration of peroxide (H2O2), citric acid, SiO2 particle and Benzotriazole (BTA) in the CMP slurry and their effects were...
Warpage is a major reliability concern for IC packages. Package structure, material property and assembly process will all impact warpage behavior, which can be characterized by 3D Finite Element Analysis (FEA). Traditionally, the FEA simulation will only analyze warpage of a free standing package with thermo-mechanical stress induced by Coefficient of Thermal Expansion (CTE) mismatch during cooling...
TiN diffusion barrier layers were deposited on SiO2/Si substrate by ALD method that employed TiCl4 and NH3 as the source and reactant gases, respectively, at a temperature range between 350°C and 500°C. Properties of films, including deposition rate, resistivity, surface roughness and chemical composition, were investigated, and performance of TiN diffusion barrier layer was also verified. Deposition...
Passive integration is one of the important issues for system miniaturization in wireless applications on different substrate. Integrated inductors were designed and realized on both silicon and planarized ceramic substrate. Planarized ceramic substrate has the advantages such as lower cost than polished ceramic substrate and has other advantages such as lower dielectric constant, higher bulk resistance...
As miniaturization is the permanent pursuit of microelectronic industry, stencil printing technology for flip chip bumping has been contributing to this trend for almost half a century. Nowadays, it's still one of the lowest cost solutions to massive manufacture of IC packaging industry. To meet the requirement of further miniaturization, this paper investigated the realization of fine pitch (about...
Micromachined technology has been widely used to reduce device size and improve performance. In this paper, our research activities on micromachined piezoelectric acoustic devices at wide frequency range, from audio microphones to ultrasonic transducers, are reviewed. These devices are based on ferroelectric thin films, and exceed the conventional acoustic devices in excellent performance, miniaturized...
Wafer level packaging (WLP) technology has been used to integrate high-Q inductor on Si substrate. These inductors consist of a thick Cu electroplated rerouting to reduce series resistance and a thick dielectric layer to separate the inductors from Si substrate. The measured results show that the peak O-factor is 30 at 4 GHz for a 0.77 nH inductor, which is good agreement with the simulated performance...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.