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This paper describes an 8-bit, 10 MSamples/second analog to digital converter, with 2V fully differential input range, which is implemented in TSMC 0.25mum CMOS technology. It achieves low power dissipation of 25mW, and the chip area is 0.56mm2. Measured performance yields a very good VTC curve and a sine wave fitting curve for 200KHz input at 10Msample/s, DNL testing of -0.2LSB-0.75LSB; INL testing...
This paper presents the design of a low input (0.75 to 1.75V) and low power dissipation pipelined CMOS ADC. The 8 bits ADC consumes 78.3mW power at 2.5V supply voltage. The DNL and INL are 0.6LSB and 0.7LSB respectively, and SFDR is 51.259dB at 195kHz input frequency. The chip area is 1.023 mm times 0.795 mm with TSMC0.25mum CMOS technology
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