The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Proposed is a two-stage amplifier exploiting recycling current-buffer Miller compensation (CBMC). By reusing the most current-consuming devices in the 1st stage as current buffer, such an amplifier not only can preserve the merits of typical CBMC implementation in creating the beneficial left-half-plane (LHP) zero, but also can avoid the drawbacks of typical CBMC scheme from degrading the power efficiency,...
This paper presents novel sub-harmonic mixer topologies for W-band automotive radar applications in 65nm CMOS technology. Working principle and performance of three kinds of topologies are analyzed and discussed with physical layout and EM simulation. The simulated performance shows a double side band noise figure of 20.8 dB and a voltage conversion gain of −8.7 dB at an RF frequency of 79.0001 GHz...
In this paper, a novel CMOS-nano hybrid reconfigurable field-prgrammable gate array architecture (rFPGA) is introduced based on resistive memory (RRAM) devices. Different from the existing crossbar-based CMOS-nano architectures, rFPGA consists of mainly 1T1R RRAM structures that can be fabricated by using a CMOS-compatible process. These devices can efficiently establish FPGA block memories. More...
This paper develops a novel reconfigurable architecture, CMOS-nanorelay FPGA (cFPGA) by integrating carbon nanorelays with CMOS devices to function as FPGA components. cFPGA is a highly efficient architecture, providing 2X density and standby power improvement along with a 30% dynamic power reduction as compared with solely CMOS FPGA circuits. This performance improvement is achieved by using 2T1N...
This paper introduces a novel CMOS-memristor hybrid reconfigurable architecture, mFPGA. Different from the existing crossbar-based CMOS-memristor architectures, mFPGA mainly consists of lTlM-like structures that can be fabricated by using a CMOS-compatible process. These devices can efficiently establish FPGA block memories. More importantly, novel CMOS-memristor routing switches are developed to...
In this paper, a novel reconfigurable architecture, cFPGA (CMOS-Nanorelay FPGA) is developed by integrating carbon nanorelays and CMOS devices to function as FPGA components. cFPGA is a highly efficient architecture, providing 2?? density and standby power improvement along with 30% dynamic power reduction as compared to the CMOS FPGA circuits. This performance improvement is achieved by using 2T1N...
In this paper, the novel mechanical switch device: suspended-gate FET is applied to FPGA development. This device offers almost an ideal subthreshold swing and a hysteretic resistance switching, opening opportunities for low-power applications. The proposed device can be used as the building block of programmable elements and memory of an FPGA. Based on this device, the proposed FPGA architecture,...
New designs of Redundant Binary full Adders are proposed for redundant binary system, and implemented using 0.18 mum CMOS technology. The proposed full adder designs require low number of transistors and show lower power dissipation and reduced time delay compared to currently available designs. These new designs can be widely used for computer arithmetic units in redundant binary systems. As case...
CMOS molecular (CMOL) circuits promise great opportunities for future hybrid nanoscale IC implementation. In this paper, a novel three dimension (3D) architecture of CMOL circuit is introduced. It eliminates the special pin requirement, enabling feasible fabrication. It also doubles the density of nanowires of the original CMOL circuit, while providing similar operation performance. This work significantly...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.