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In this paper, we report on the recent development of a 32-channel low-noise front-end readout ASIC for cadmium zinc telluride (CdZnTe) X-ray and -ray detectors. Each readout channel includes a charge sensitive amplifier, a CR-RC shaping amplifier and an analog output buffer. The readout ASIC is implemented using TSMC mixed-signal CMOS technology, the die size of the prototype...
This paper presents a low-noise front-end readout application specific integrated circuit (ASIC) for CZT detectors. A cascode amplifier based on split-let topology is selected to realize the charge-sensitive amplifier (CSA) to achieve low noise performances. A leakage-current-compensation circuit is added to suppress the leakage current of from 0 to 10 nA. The output of the CSA is connected to a slow...
This paper presents the design of a low-noise multi-channel front-end readout chip integrated with a high-resolution TDC. It is foreseen to be used as front-end readout electronics of Avalanche Photo Diodes (APD) dedicated to a small animal Positron Emission Tomography (PET) system. The architecture of the chip is depicted. Two prototype chips, a ten-channel front-end chip and a three-channel high-resolution...
This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum2 and 0.54mum 2 SRAM cells, optimized for performance and density, respectively. The key focus of this technology has been low cost, process simplicity and...
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