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A 12-bit 20-MS/s charge redistribution successive approximation register analog-to-digital converter in a 65-nm CMOS technology is presented in this paper. To address the issue of long DAC settling time in bit-conversion, an improved internal clock generator is proposed. In addition, a novel SAR controller is introduced to minimize the critical path and improve the conversion speed. Simulation results...
In this paper, a digital calibration scheme is proposed to correct phase mismatch among the multi-phase inputs of the pulse combiner to suppress the spurs at the output of the multi-modulus fractional frequency local oscillator divider. Compared with the conventional design, the proposed calibration scheme utilizes most correlated comparison algorithm to reduce convergence time significantly. The...
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