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A 12-bit 20-MS/s charge redistribution successive approximation register analog-to-digital converter in a 65-nm CMOS technology is presented in this paper. To address the issue of long DAC settling time in bit-conversion, an improved internal clock generator is proposed. In addition, a novel SAR controller is introduced to minimize the critical path and improve the conversion speed. Simulation results...
A novel frequency divider for Quantization Noise (QN) suppression in fractional-N phase-locked loops (PLLs) is presented in this paper. The proposed Multi-Modulus Frequency Divider (MMFD) utilizes a novel glitch-free divide-by-0.5/1/1.5/2 cell to reduce the frequency division step to 0.5 and the quantization noise induced by ΔΣ modulation is thus suppressed by additional 6dB. The circuit is designed...
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