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In this paper, we present a novel non-classical NMOS transistor with elevated body and spacer to replace the conventional PMOS for CMOS circuits. By calibrating the parameters from the real measurement for the simulations, the novel non-classical NMOS transistor shows a PMOS-like behavior. The proposed unipolar CMOS can reduce the propagation delay time (TP) and power dissipation (PD). The simulation...
<?Pub Dtl?>A quadrature voltage-controlled oscillator was designed with back-gate coupling and embedded self body-biasing and implemented with the TSMC 0.18 1P6M CMOS technology. Without using any extra negative bias-pin in the current-reuse structure, this embedded body-bias schema makes the switching transistors become forward body-biased in the duration of turn-on. It is not only...
A 1.8-V 250-mA CMOS low-dropout regulator (LDO) with a current-efficiency rail-to-rail buffer to enhance load regulation is presented. The proposed buffer provides a push-pull output stage for driving pass device and pushes the parasitic pole far beyond the unity-gain frequency to improve phase margin of the LDO loop response. The proposed LDO has been implemented in a 0.35-μm CMOS process technology...
This paper presents a new low-power charge-recycling dynamic programmable logic array (PLA). The charge recycling PLA reduces the power consumption in product lines by recycling the previously used charge. The proposed dynamic PLA, product lines swing voltage is lowered by the charge recycling circuit between on adjacent product lines. Power consumption in product lines can be reduced theoretically...
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